This disclosure relates to data processing and data storage, and more specifically, to non-volatile memory storing multiple bits of data per cell. Still more particularly, the disclosure relates mitigating read errors following programming in a non-volatile memory system storing multiple bits of data per cell.
NAND flash memory is an electrically programmable and erasable non-volatile memory technology that stores one or more bits of data per memory cell as a charge on the floating gate of a transistor or a similar charge trap structure. The amount of charge on the floating gate modulates the threshold voltage of the transistor. By applying a proper read voltage and measuring the amount of current, the programmed threshold voltage of the memory cell can be determined and thus the stored information can be detected. Memories storing one, two, three and four bits per cell are respectively referred to in the art as Single Level Cell (SLC), Multi-Level Cell (MLC), Three Level Cell (TLC), and Quad Level Cell (QLC) memories. In a typical implementation, a NAND flash memory array is organized in blocks—of physical memory, each of which includes multiple physical pages each in turn containing a multiplicity of memory cells. By virtue of the arrangement of the word and bit lines utilized to access memory cells, flash memory arrays have generally been programmed on a page basis, but erased on a block basis.
In multi-level (i.e., MLC, TLC and QLC) NAND flash memory, information is stored by programming the memory cells to various quantized threshold voltage levels according to the device's programming algorithm, which maps the binary bit values to discrete threshold voltage levels. In response to a page read command, the binary bit values are retrieved by applying appropriate read voltages that divide the programmed threshold voltage window into discrete regimes and by then applying a reverse mapping between the detected threshold voltage levels and the corresponding binary bit values.
In multi-level flash memory, there is period following programming during which the programmed threshold voltage distributions for a page settle to their stable state. During this period, the page generally cannot be read from the flash memory without an increased number of read errors. For example, in MLC NAND flash memory, data is written in pages that form page pairs (referred to in the art as “upper page” and “lower page”) which share the same physical cells on a word-line. Programming is typically accomplished utilizing a two-step process in which the lower page is first programmed with only one bit of information resulting in two threshold voltage distributions. In the second step, two bits of information are programmed in the upper and lower pages, resulting in four threshold voltage distributions. In general, the lower and upper pages forming a page pair are not consecutive in terms of programming order, and multiple other pages are instead interleaved in a way to control cell-to-cell interference. As a result of this conventional two-step programming process, correct readout of both the upper page and the associated lower page can be dependent on waiting for a delay period after programming the later programmed upper page.